? semiconductor components industries, llc, 2015 january, 2015 ? rev. 2 1 publication order number: NCP81166/d NCP81166, NCP81166a synchronous buck mosfet drivers the NCP81166/a is a high performance dual mosfet gate driver optimized to drive the gates of both high?side and low?side power mosfets in a synchronous buck converter. 2mm x 2mm dfn8 package allows for space?optimized board layout. zero current detect feature allows for a high?efficiency solution even at light load conditions. pre?ovp feature aids in protecting the load in the event of a short across the high?side fet. v cc uvlo ensures the mosfets are off when supply voltages are low. a bi?directional enable pin provides a fault signal to the controller when a pre?ovp or uvlo fault is detected. features ? space?efficient 2 mm x 2mm dfn8 thermally?enhanced package ? v cc range of 4.5 v to 13.2 v ? integrated bootstrap diode ? pre?ovp function protects load during hs fet short ? NCP81166: 2.25 v sw trip threshold ? NCP81166a: 1.8 v sw trip threshold ? zero current detect function provides power saving operation during light load conditions ? bi?directional enable feature pulls enable pin low during pre?ovp and uvlo faults ? 5 v tri?state pwm logic ? adaptive anti?cross?conduction circuit protects against cross?conduction during fet turn?on and turn?off ? output disable control turns off both mosfets via enable pin ? vcc undervoltage lockout ? direct interface to asp 1252, asp1400 and other compatible pwm controllers ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? power solutions for desktop systems device package shipping ? ordering information NCP81166mntbg dfn8 (pb?free) 3000 / t ape & reel http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. dfn8 mn suffix case 506cn marking diagram xx = specific device code ce for NCP81166 ch for NCP81166a m = date code = pb?free device xxm 1 1 NCP81166amntbg dfn8 (pb?free) 3000 / tape & reel (note: microdot may be in either location)
NCP81166, NCP81166a http://onsemi.com 2 figure 1. pin diagram bst drvh sw drvl pwm nc en vcc 1 gnd (top view) 9 bst pwm logic drvh sw anti?cross conduction vcc drvl vcc en fault uvlo pre?ov zcd detection figure 2. block diagram table 1. pin descriptions pin no. symbol description 1 pwm control input. the pwm signal has three distinctive states: low = low side fet enabled, mid = diode emu- lation enabled, high = high side fet enabled. 2 nc no connect. there is no electrical connection from this pin to the die. externally connecting this pin to ground will not affect the functionality of the part. 3 en logic input. a logic high to enable the part and a logic low to disable the part. pin is internally pulled low dur- ing pre?ovp and uvlo faults. 4 vcc power supply input. connect a bypass capacitor (1 f) from this pin to ground. 5 drvl low side gate drive output. connect to the gate of low side mosfet. 6 sw switch node. connect this pin to the source of the high side mosfet and drain of the low side mosfet. 7 drvh high side gate drive output. connect to the gate of high side mosfet. 8 bst floating bootstrap supply pin for high side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 9 gnd bias and reference ground. all signals are referenced to this node.
NCP81166, NCP81166a http://onsemi.com 3 figure 3. application circuit vreg_sw1_hg vccp tp3 vreg_sw1_out vreg_sw1_lg tp6 tp7 tp8 tp4 tp1 tp2 tp5 ntmfs4851n ntmfs4851n q9 q10 ntmfs4821n q1 NCP81166/a bst pwm en vcc hg sw gnd lg pad dron pwm csn11 csp11 c1 c2 c3 ce9 l r3 c6 r164 12v_power r1 r143 c4 0.027uf 0.0 1.02 c5 1uf r142 0.0 0.0 2.2 2700pf 235nh 4.7uf 4.7uf 4.7uf 390uf + jp13_etch jp14_etch table 2. absolute maximum ratings pin symbol pin name v max v min vcc main supply voltage input 15 v ?0.3 v bst bootstrap supply voltage 35 v wrt/ gnd 40 v 50 ns wrt/ gnd 15 v wrt/ sw ?0.3 v wrt/sw sw switching node (bootstrap supply return) 35 v 40 v 50 ns ?5 v ?10 v (200 ns) drvh high side driver output bst+0.3 v ?0.3 v wrt/sw ?2 v (<200 ns) wrt/sw drvl low side driver output vcc+0.3 v ?0.3 v dc ?5 v (<200 ns) pwm drvh and drvl control input 6.5 v ?0.3 v en enable pin 6.5 v ?0.3 v gnd ground 0 v 0 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. thermal information (all signals referenced to agnd unless noted otherwise) symbol parameter value unit r ja thermal characteristic (note 1) 74 c/w t j operating junction temperature range* (note 2) ?40 to 150 c t a operating ambient temperature range* ?10 to +125 c t stg maximum storage temperature range ?55 to +150 c msl moisture sensitivity level 1 * the maximum package power dissipation must be observed. 1. i in 2 cu, 1 oz thickness. 2. operation at ?40 c to ?10 c guaranteed by design, not production tested.
NCP81166, NCP81166a http://onsemi.com 4 table 4. electrical characteristics ( unless otherwise stated: ?10 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst?swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter test conditions min. typ. max. units supply voltage vcc operation voltage 4.5 13.2 v pre?ovp threshold 2.75 3.2 v undervoltage lockout vcc start threshold 3.8 4.35 4.5 v vcc uvlo hysteresis 150 200 250 mv output overvoltage trip threshold at startup vcc > pre?ovp threshold NCP81166 NCP81166a 2.1 1.65 2.25 1.80 2.4 1.95 v supply current normal mode icc + ibst, en = 5 v, pwm = osc, fsw = 100 khz, cload = 3 nf for drvh, 3 nf for drvl 10 ma standby current icc + ibst, en = gnd 0.5 1.4 ma standby current i cc + i bst , en = high, pwm = low, no loading on drvh & drvl 2.0 ma standby current i cc + i bst , en = high, pwm = high, no loading on drvh & drvl 2.0 ma bootstrap diode forward v oltage v cc = 12 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input high 3.4 v pwm mid?state 1.3 2.7 v pwm input low 0.7 v zcd blanking timer 250 ns high side driver (vcc = 12 v) output impedance, sourcing current vbst ? vsw = 12 v 1.9 3.0 output impedance, sinking current vbst ? vsw = 12 v 1.0 1.7 drvh rise time tr drvh v vcc = 12 v, 3 nf load, vbst?vsw = 12 v 16 30 ns drvh fall time tf drvh v vcc = 12 v, 3 nf load, vbst?vsw = 12 v 11 25 ns drvh turn?off propagation delay tpdl drvh c load = 3 nf 8.0 30 ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 30 ns sw pull down resistance sw to pgnd 45 k drvh pull down resistance drvh to sw, bst?sw = 0 v 45 k high side driver (vcc = 5 v) output impedance, sourcing current vbst ? vsw = 5 v 2.5 output impedance, sinking current vbst ? vsw = 5 v 1.6 drvh rise time tr drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 30 ns drvh fall time tf drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 27 ns drvh turn?off propagation delay tpdl drvh c load = 3 nf 20 ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 27 ns sw pull down resistance sw to pgnd 45 k
NCP81166, NCP81166a http://onsemi.com 5 table 4. electrical characteristics ( unless otherwise stated: ?10 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst?swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter units max. typ. min. test conditions high side driver (vcc = 5 v) drvh pull down resistance drvh to sw, bst?sw = 0 v 45 k low side driver (vcc = 12 v) output impedance, sourcing current 2.0 3.0 output impedance, sinking current 0.7 1.5 drvl rise time tr drvl c load = 3 nf 16 35 ns drvl fall time tf drvl c load = 3 nf 11 20 ns drvl turn?off propagation delay tpdl drvl c load = 3 nf 35 ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 8.0 30 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 45 k low side driver (vcc = 5 v) output impedance, sourcing current 2.5 output impedance, sinking current 1.0 drvl rise time tr drvl c load = 3 nf 30 ns drvl fall time tf drvl c load = 3 nf 22 ns drvl turn?off propagation delay tpdl drvl c load = 3 nf 27 ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 12 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 45 k en input input voltage high 2.0 v input voltage low 1.0 v hysteresis 500 mv normal mode bias current ?1 1 a enable pin sink current 4 30 ma propagation delay time 20 40 ns sw node sw node leakage current 20 a zero cross detection threshold v oltage sw to ?20 mv, ramp slowly until bg goes off (start in dcm mode) (note 3) ?6 mv table 5. decoder truth table pwm input zcd drvl drvh pwm high zcd reset low high pwm mid positive current through the inductor high low pwm mid zero current through the inductor low low pwm low zcd reset high low 3. guaranteed by design; not production tested.
NCP81166, NCP81166a http://onsemi.com 6 figure 4. timing diagram figure 5. logic diagram pwm drvh?sw drvl il pwm drvh?sw drvl 90% tpdl drvl tf drvl 1 v 10% tpdh drvh tr drvh 90% 10% 10% 90% tpdl drvh tf drvh tpdh drvl tr drvl 1 v 10% 90%
NCP81166, NCP81166a http://onsemi.com 7 applications information description the ncp81 166/a gate driver is a single phase mosfet driver designed for driving n?channel mosfets in a synchronous buck converter topology. the NCP81166 is designed to work with the on semiconductor?s asp1252 controller and the NCP81166a is designed to work with on semiconductor?s asp1400 controller. low?side driver the low?side driver is designed to drive a ground?referenced low?r ds(on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vcc and gnd pins. there is a 45 k pull?down resistor connected between drvl and gnd. high?side driver the high?side driver is designed to drive a floating low?r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the sw pin. there is a 45 k pull?down resistor connected between drvh and sw. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. when the NCP81166/a is starting up, the sw pin is held at ground, allowing the bootstrap capacitor to charge up to vcc (minus the diode forward voltage) through the bootstrap diode. when the pwm input is driven high, the high?side driver will turn on the high?side mosfet, using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the sw pin rises. when the high?side mosfet is fully turned on, sw will settle to vin and bst will settle to vin + vcc (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the high?side driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used for c bst . power supply decoupling the NCP81166/a can source and sink relatively large currents to the gate pins of the mosfets. in order to maintain a constant and stable supply voltage, a low?esr capacitor should be placed near the vcc and gnd pins. a mlcc between 1 f and 4.7 f is typically used. undervoltage lockout drvh and drvl are low until vcc reaches the vcc uvlo threshold, typically 4.35 v. once vcc reaches this threshold, the pwm signal will control drvh and drvl. there is a 200 mv hysteresis on vcc uvlo. there are pull?down resistors on drvh, drvl and sw to prevent the gates of the mosfets from accumulating enough charge to turn on when the driver is powered off. pre?overvoltage protection the pre?overvoltage protection (pre?ovp) feature is used to protect the load if there is a short across the high?side fet. when vcc is greater than 2.75 v, the voltage on sw is monitored. during startup, if sw is determined to be greater than output overvoltage trip threshold, drvl will be latched high to turn on the synchronous fet and provide a path from vin to ground. this also pulls the en pin low. to exit this behavior, power to the driver must be turned off (vcc less than uvlo rising minus uvlo hysteresis) and then vcc powered back on. when vcc rises above uvlo rising and en is above en hi , the gate driver enters normal pwm operation (drvh and drvl respond to the pwm signal) and the pre?ovp function is disabled. bi directional en signal the enable pin (en) is used to disable the drvh and drvl outputs to prevent power transfer. when en is above the en hi threshold, drvh and drvl change their states according to the pwm input. fault modes, such as pre?ovp and uvlo, turn on an internal mosfet that pulls the en pin towards ground. by connecting en to the dron pin of a contro ller, the controller is alerted when the driver encounters a fault condition. pwm input and zero cross detect (zcd) switching pwm between logic?high and logic?low states will allow the driver to operate in continuous conduction mode as long as vcc is greater than the uvlo threshold and en is high. the threshold limits are specified in the electrical characteristics table in this datasheet. when pwm is set above pwm hi , drvl will first turn off after a propagation delay of tpdl drvl . to ensure non?overlap between drvl and drvh, there is a delay of tpdh drvh from the time drvl falls to 1 v, before drvh is allowed to turn on. when pwm falls below pwm lo , drvh will first turn off after a propagation delay of tpdl drvh . to ensure non?overlap between drvh and drvl, there is a delay of tpdh drvl from the time drvh ? sw falls to 1 v, before drvl is allowed to turn on. when pwm enters the mid?state voltage range, pwm mid , drvl goes high after the non?overlap delay, and stays high for the duration of the zcd blanking timer and an 80 ns de?bounce timer. once these timers expire, sw is monitored for zero current detection and pulls drvl low once zero current is detected. layout guidelines layout for dc?dc converter is very important. the bootstrap and vcc bypass capacitors should be placed as close as to the driver ic as possible.
NCP81166, NCP81166a http://onsemi.com 8 connect the gnd flag to local ground plane. the ground plane can provide a good return path for gate drives and reduce the ground noise. this connection also allows for good heat dissipation. to minimize the ground loop for the low?side mosfet, the gnd flag should be close to the low?side fet source pin. the gate drive trace should be routed to minimize the length, the minimum recommended width is 20 mils.
NCP81166, NCP81166a http://onsemi.com 9 package dimensions dfn8 2x2, 0.5p case 506cn issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.15 c 0.10 c 0.08 a1 seating plane 8x note 3 b 8x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 b 0.20 0.30 d 2.00 bsc d2 1.50 1.70 e 2.00 bsc e2 0.80 1.00 e 0.50 bsc l 0.17 0.38 1 4 8 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 1.05 2.30 1 dimensions: millimeters 0.50 8x note 4 0.30 8x detail a a3 0.20 ref a3 a detail b a1 a3 ??? ??? ??? 0.15 outline package e recommended k 0.27 ref 5 1.75 k alternate construction l1 detail a l alternate constructions l e/2 a m 0.10 b c m 0.10 c on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCP81166/d p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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